Controller Synthesis in Hardware Accelerator Design for video Segmentation

Video segmentation techniques have so far been widely used for a range of applications such as MPEG-4 encoding and automatic surveillance system. Historically, algorithms developed for such applications have been restricted to less complex and robust solutions implemented on computers. As a consequence, most systems were either too slow or succeeded under very controlled situations. In this project, a more robust algorithm based on statistical background model is studied with the intention of hardware implementation for real time system. Specific architectures are explored trying to address the computation issues identified in the algorithm. Meanwhile, in order to reduce the design effort for the controller design in such system, modifications to an existing controller synthesis tool are made to support the design flow from algorithm specification to RTL level VHDL.